Chemical mechanical planarization (CMP) is an essential polishing process in semiconductor manufacturing. Advances in memory technology, including increased capacity and performance, have increased the importance of electronic packaging. In heterogeneous integration, the interposer acts as an important intermediary between the logic die and the substrate, solving numerous I/O bump problems in high-bandwidth memory (HBM) and logic chips. Traditionally, board-to-memory connections were made through wire bonding, which required additional space for wire connections and introduced latency due to extended signal transmission paths. A through-type approach has emerged as a solution that can significantly reduce waiting time and installation space by improving space efficiency and enabling vertical connections without extending wiring. Due to these new approaches, the importance of CMP is reemerging. Implementation of this important process requires precise control of the CMP dishing/protrusion of bonding surfaces. Improper selection of Cu pad dishing/protrusion can cause problems such as increased RC delay time and signal short circuit in the wiring. In this paper, we proposed a strategy to control dishing using CMP, especially for Through-glass-via (TGV).