Solid Oxide Fuel Cells (SOFCs) are energy conversion devices known for their significantly higher power density compared to other fuel cell types. However, their high operating temperatures pose challenges related to thermal stability. To address this, research is focusing on Low-Temperature SOFCs (LT-SOFCs), which function at lower temperatures and exhibit enhanced electrochemical performance. While various electrode materials are utilized in SOFCs, platinum (Pt) stands out for its excellent electronic conductivity and catalytic activity. Unfortunately, at the operating temperatures of SOFCs, Pt tends to agglomerate, leading to a rapid reduction in the triple phase boundary (TPB) and a subsequent decline in electrochemical reactions. In this study, LT-SOFCs were fabricated with a Praseodymium Oxide (PrOx) capping layer applied to a porous Pt cathode using sputtering, with various thicknesses achieved by adjusting the deposition time. The electrochemical performance of the LT-SOFCs was measured at 500^oC. Additionally, the degradation behavior of the LT-SOFCs was assessed by applying a constant voltage of 0.5 V for 48 hours. Scanning Electron Microscopy (SEM) analysis was also conducted on the PrOx capping layer thin films under the same operating conditions.

This study introduces a novel retainer ring design aimed at mitigating the edge effect during chemical mechanical planarization. The innovative design features an arch-shaped geometry that creates a bending effect, thereby reducing excessive pressure on the wafer's edge. A two-dimensional axisymmetric finite element model was developed, and simulation data were utilized to create a metamodel. Multi-objective optimization was conducted using an evolutionary algorithm, focusing on the normal contact stress on the wafer surface. Representative Pareto-optimal designs were analyzed to assess the distribution of normal contact stresses. The results demonstrated that the proposed design significantly reduced peak normal stresses and enhanced stress uniformity, especially at the wafer edge. This optimized retainer ring is anticipated to improve wafer edge quality and increase semiconductor yield.