The demand for high-speed processing and big data has accelerated the adoption of three-dimensional integrated circuits (3D ICs), where interposers serve as essential components for chip-to-chip connectivity. However, silicon interposers using the through-silicon via (TSV) technology have structural limitations. As alternatives, glass-based interposers employing the through-glass via (TGV) technology are gaining attention. This study explored the fabrication of via holes in glass substrates using the selective laser etching (SLE) process. A spatial light modulator (SLM) was used to generate donut- shaped bessel beams by inserting an image pattern without relying on phase modulation. The machinability of via holes fabricated with these beams was compared to that of holes formed using phase-modulated beams. Effect of pulse energy on taper angle was also investigated. Hourglass-shaped holes were observed at lower pulse energies. However, taper angles approaching 90° were observed at higher energies, indicating an improved verticality.

Chemical mechanical planarization (CMP) is an essential polishing process in semiconductor manufacturing. Advances in memory technology, including increased capacity and performance, have increased the importance of electronic packaging. In heterogeneous integration, the interposer acts as an important intermediary between the logic die and the substrate, solving numerous I/O bump problems in high-bandwidth memory (HBM) and logic chips. Traditionally, board-to-memory connections were made through wire bonding, which required additional space for wire connections and introduced latency due to extended signal transmission paths. A through-type approach has emerged as a solution that can significantly reduce waiting time and installation space by improving space efficiency and enabling vertical connections without extending wiring. Due to these new approaches, the importance of CMP is reemerging. Implementation of this important process requires precise control of the CMP dishing/protrusion of bonding surfaces. Improper selection of Cu pad dishing/protrusion can cause problems such as increased RC delay time and signal short circuit in the wiring. In this paper, we proposed a strategy to control dishing using CMP, especially for Through-glass-via (TGV).